The present invention relates to a method for fabricating a semiconductor device; and, more particularly, to a method for forming via holes having different depths by conductive layers constructed in a multi-layered stacking structure.
Generally, determination of the size of an integrated circuit (IC) chip, with use of a device in which the size is less than the sub-microns, depends on a layout rule that enables the manufacturing process. Also, the pitch of a metal for wiring between devices generally determines the IC chip size.
A multi-layered metal wiring technique is one proposed approach for solving the above-described limitation in the determination of the IC chip size by providing flexibility of the layout and augmenting the degree of integration while reducing the area of a chip. Ultimately, with this developed technique, it is possible to attain a device with multi-functions and high integration.
In addition to metal wiring, other conductive layers such as bit lines, word lines, storage nodes and so forth are also vertically arrayed in a multi-layer structure.
FIGS. 1A and 1B are cross-sectional views illustrating a process for forming via holes allocated at layers having substantially different thicknesses in accordance with the prior art and a further explanation will be provided with reference to FIGS. 1A and 1B.
A first conductive layer 11 is formed on a substrate board (not shown) and a first antireflection layer 12 is formed thereon. A first insulating layer 10 is formed on the first conductive layer 11 and the first antireflection layer 12, and a planarization process is applied to the first insulating layer 10. Formation of a second conductive layer 14, a second antireflection layer 15 and a second insulating layer 13 on top of the first insulating layer 10, which is, in turn, followed by another subsequent formation of a third conductive layer 17, a third antireflection layer 18 and a third insulating layer 16 thereon. The first to the third antireflection layers 12, 15 and 18 are designated for preventing irregular reflections, which occur due to photo exposure during a photo-etching process for forming each pattern with the first to the third conductive layers 11, 14 and 17, and the thickness of each antireflection layer 12, 15 and 18 is generally uniform. This constructional scheme represents a multi-layered metal wiring, and one mask is used to make contacts for connecting multi-layered wiring structures for the purpose of simplifying a manufacturing process. That is, as shown in FIGS. 1A and 1B, via holes are formed with one photoresist pattern 19 formed by an exposure process with one mask.
Next, referred to FIG. 1B, the photoresist pattern 19 acts as an etch mask in order to form via holes 20A, 20B and 20C exposing the first to the third conductive layers 11, 14 and 17.
Meanwhile, via holes formed simultaneously through a photo etching process have different depths, because the thickness of the etch target to each conductive layer 11, 14 and 17 is different. Moreover, it is, therefore, inevitable that the conductive layers 14 and 17 are excessively etched in the case where the third via hole 20C which has a depth which is relatively large compared to the other two via holes, because the etch target is determined by the condition for forming the via hole 20C. Reference numerals 21 and 22 in FIG. 1B represent the loss of the conductive layers 17 and 14.
On the other hand, in case where the etch target is determined by the upper conductive layer 17 or 14 in the etching process to prevent a loss of the top conductive layers due to excessive etching, there results in a bad contact at the bottom conductive layer 11.
It is, therefore, an object of the present invention to provide a method for fabricating a semiconductor device that is capable of obtaining a proper process margin during the process for forming via holes in a multi-layered stacking structure having different depths without requiring additional process steps.
In accordance with one aspect of the present invention, there is provided a method for fabricating a semiconductor device, including the steps of: forming a first conductive layer; forming a first etching protection layer on the first conductive layer; forming a first insulating layer; forming a second conductive layer on the first insulating layer; forming a second etching protection layer on the second conductive layer, wherein the etching protection efficiency of the second protection layer is higher than the first etching protection layer; forming a second insulating layer; and forming first and second via hole respectively exposing the first and the second conductive layer by selectively etching the first and the second insulating layer.
In accordance with another aspect of the present invention, there is provided a method for fabricating a semiconductor device, including the steps of: forming a first conductive layer; patterning the conductive layer with a first antireflection layer formed on the first conductive layer; forming a first insulating layer; forming a second conductive layer on the first insulating layer; patterning the second conductive layer with a second antireflection layer formed on the second conductive layer, wherein a etching-protection efficiency of the second antireflection layer is higher than the first antireflection layer; forming a second insulating layer; and forming a first and a second via hole respectively exposing, the first and the second conductive layer by selectively etching the first and the second insulating layer.
The present invention provides the advantage of preventing degradation of the semiconductor properties that occurs due to an excessive etching of the conductive layer when simultaneously forming the via holes in a multi-layered structure that has significant depth differences by providing variations in the thickness of the antireflection layers allocated on the conductive layers in the multi-layered structure.